Jeu instruction cpu Cpu instruction set definition
processor design steps

Don't forget the flags !

In the 32 registers bank, R02 will be reserved for flags. SC91-A has 32 bits used for status that may be changed by standard instructions. All of these bits are not used so the status/flag register will be able to be extend later.

Flag status register (R02)
31302928272625242322 21201918171615141312 11109876543210
EI Not used 0PC32C16C8O32O16O8 S32S16S8Z

Specific registers

In the 32 registers, some of thel have to be reserved for specific usage, as for flags. It exists some other one :

The others registers are not reserved. They are used for a general use.

Instruction set definition

SC91-A processor has a minimum instruction set ; first, it has to allow logical and arithmetical operations, memory read/write instruction, rotations, conditional and unconditional jump, procedure call and the no operation one. Here are the main instruction family.

As I decided to code instructions on 32 bits, this will allow to encode in every instructions two source operands and one destination. So instructions will have up to 3 registers operands. These registers will be identified by dd for the destination ans nn or mm for source operand. When a register will used as a memory pointer it will be preceded by a &

Register loading

Registers may be intialized with a diect value or after a memory read. As instructions width is 32 bits, it will not possible to load a register in a single step so the direct loading instruction will just allow a 16 bits loading. This direct loading instruction will be LOADd and it will load a direct value v into the dd register.
To allow to load a 32bits value into the register, instruction will have different available mode :

Impact flags : P, Z, C16, C8, S32, S16, S8, O8, O16; O32 hos no sense.

Summary :

Usage : LOADd Rdd,dir16,mode
Exemple : LOADd R31,0x1234,low
Résuls : R31 <= 0x1234

Instruction LOADm will be used for register initialization for a memory read. This one load into register Rdd the memory value read at address inicated by register Rmm. mode parameter will indicate data read width between 8, 16 or 32 bits signed or not; this value will be followed by u or s to indicate signed or unsigned option.

Flags impact : P, Z, C16, C8, S32, S16, S8, O8, O16; O32 has no sense.

Summary :

Usage : LOADm Rdd,&Rmm,mode
Exemple : LOADm R31,&R30,16u
Résults : R31 <= unsigned word ptr [R30]
                R31(b31 à b16) <= 0 et R31(b15 à b0) <= [R30](b15 à b0)

Registers may be loaded from an other register with instruction LOADr. Register Rdd receives the value of Rnn register. The field mode allow to select the width of the copy : 8, 16 or 32 bits as seen precedently.

Flags impact : P, Z, C16, C8, S32, S16, S8, O8, O16; O32 has no sense.

Usage : LOADr Rdd,Rnn,mode
Exemple : LOADr R31,R30,16s
Results : R31 <= (signed word)(R30)
                R31(b31 à b16) <= R30(b15) et R31(b15 à b0) <= R30(b15 à b0)

Memory writing

LOAD/STORE architecture will only allow STORE instruction to write data into memory. As for memory read, it is necessary to precise the width of the data (registers are all 32 bits). But it is not necessary to precise if value is signed or not as destination size is equal or less than source. So mode are 8, 16 or 32.

No flag impact.

Usage : STORE &Rmm,Rnn,mode
Exemple : STORE &R31,R30,16
Results : [R31] <= (word)(R30)
                [R31] <= R30(b15 à b08) et [R31+1] <= R30(b07 à b0) Big-Endian
Logical operations
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