Simple-CPU creation steps
As I do this work with a pedagogical objective for me and I hope fr you too, I'd to comment each steps of
the way I took to build thisp processor. I won't follow a specific design way as it may exists in some
books, so the following step will follow that I think is a logical way. My own thinking way.
So, I'm going to start with a macro desciption of what should be Simple-CPU, its genral architecture. Then what it should be able to do : its instruction set capabilities. These step will be enought to describe a detailed architecture of each internal componentof the processeur. To finish, I will describe VHDL coding of the processor.
First step : Finding it a name !
Be sure that this phase may be the most important one ! Something commercial, evocating dreams, technology ,synonim of power .... I hope, all of these are missed : it will be simple-cpu, just because I like it ! And for this only one reason, If you would produce it as a real component, I'd you to call it with that name : SC91-1 for Simple-CPU (designed by) Disk91 - A (as first revision).
Second step : Architecture description
Interesting things start now ! This step will describes main line of what the target processor may be. A
processor is mainly describes by its instruction type that should be RISC or CISC.
RISC processor has Reduced Instruction Set so it has a limited number of differents instructions. All of these are executing simple tasks. Addressing methods are also limited. Generaly they have fixed width instuction encoding and execution of each may take only one cycle.
CISC processor has Complex Instruction Set so it has, in opposition, a large number of instructions. They are able to execute complexe treatments. Generaly, they use variable instruction length and processing time depends on what instruction has to do ; it may took many cycles. For exemple, CMPS instruction in a 80x86 instruction set may increment two registers and compare two data indiectly read from memory !
SC91-1 will be a RISC processor and it will have as less instructions as possible. All of these will need only one cycle for execution. Instruction width will be fixed to one word length. Memory access will be limited to a Load-Store model. So the only one way to access memory will be using a dedicated LOAD instruction for reading and a STORE one for writting.
Next choice is the word length : This parameter may defined processor bit width : memory size, computing size, bus size, instruction size. Actual current processors are 32 bits width when the new generation is 64 bits. So have a look on what these size impact on :
- Memory size : This point is the main reason of 32 bits to 64 bits growing
- Bus width : Impact data transfer bit rate
- Computing size : Sources and result size, low impact just reduce computation time
- Instruction size : Impact program size and memory optimization, low impact actually
- Gates need : Impact design size, consumtion, price ...
- Component pads : Impact produciton cost, board design complexity
So, Simple-CPU may be able to run light applications and classic operating systems. Its memory size may so
high than some méga-octets. A 32 bit solution may so a good choice. This kind of design will required a lot
of gates but as current programmable components are big enought it should be right. As an illustration, Spartan
component used to realized it has 200.000 gates that is nearly the size of a well knowned CISC processor named
This choice impacts operand size and so register size. It impact the number of registers : these one need a lot of flip flop. But as this number of register is an important optimization way, mainly in a Load-Store architecture, I think about having 32 registe. In fact, registers may limit memory access that has a slow bitrate that is the main actual problem in current computers. (But this doesn't solve instruction memory access for sure !).
SC91-A will be based on a 32 bits architecture with 32 registers. That is representing 1024 flip flop in the designed. This may be compatible with the design targeted component. A lower version of the SC91-A may be also defined with only 16 registers for an industrial low cost target.
To finish, I have to defined if this CPU will be little or big endian : does it write value little-end first or big-end first ? I 'm prefering the second one as this mode is knowned as the network mode. This will reduce swap step before and after reading data in a network. So big end of numbers will be stored at the lowest memory address.
These elements of architecture allow us to see the next step of the design that is the choice of what instructions this processor may be able to process.